1. Field of the Invention
The present invention relates to a high frequency semiconductor device fabricated using a field effect transistor (also referred to as a "FET" in this specification), in particular, a FET formed on a semi-insulating GaAs substrate or an InP substrate; and a method for fabricating the same. The term "high frequency semiconductor device" herein is used as a general term referring to various types of high frequency devices including a power amplifier, a low-noise amplifier, and a mixer.
2. Description of the Related Art
Due to its excellent high frequency characteristics, demand for a gallium arsenide (GaAs) FET is significantly increasing as a device to be used in a mobile communication device such as a portable telephone. Among others, a GaAs power FET to be used as a power amplifier component in an amplifier for transmission or the like has undergone rapid progress by utilizing such characteristics as its low voltage operation, low power consumption, and low distortion. Moreover, in the near future, a radio system using a millimeter wave band, in addition to a microwave band, is to be utilized for commercial purposes. Therefore, demand for a higher frequency and demand for a lower cost need to be satisfied in one device at the same time.
Hereinafter, a high frequency semiconductor device according to a conventional technique will be described.
FIG. 17 is a plan view schematically illustrating a conventional high frequency GaAs power FET chip 1410.
The FET chip 1410 employs a comb-shaped electrode structure in order to increase the size of a FET included therein. More specifically, a region 1400 surrounded by a dashed line in the FET chip 1410 corresponds to a unit FET. The unit FET includes a source electrode 1401, a gate electrode 1402, and a drain electrode 1403. The FET chip 1410 has, for example, six of the thus formed unit FETs.
The source electrode 1401, the gate electrode 1402, and the drain electrode 1403 are connected to a source electrode pad 1407, a gate electrode pad 1408, and a drain electrode pad 1409, using a source extension line 1404, a gate extension line 1405, and a drain extension line 1406, respectively. Upon mounting the FET chip 1410 on a package, the electrode pads 1407 to 1409 are connected to respective electrodes of the package, for example, by bonding wires.
In general, in the case where the FET is operated at a high power, it is necessary to allow heat generated by such operation to efficiently escape to the outside of the chip. In addition, in order for the FET to operate in a frequency such as a microwave band or a millimeter wave band, it is necessary to reduce a source inductance of the FET. As a method for overcoming these problems, the article "Ku-Band Power Amplifier using Pseudomorphic HEMT Devices for Improved Efficiency" (1991, IEEE MTT-S Digest, pp.819-821) by D. Helms et al. describes that both an improvement in the heat releasing property and a reduction in the source inductance can be realized by (1) grinding a semiconductor substrate to reduce the thickness thereof and (2) providing a via hole immediately below a source electrode and filling the via hole with a metal material.
According to the method disclosed in the aforementioned article, however, a reduced production yield results since cracking of a wafer and the like may be caused by the process of grinding the semiconductor substrate (especially the GaAs substrate) to a thin thickness and forming the via hole.
As a method for mounting a high frequency semiconductor device which prevents the problems as described above from occurring, there is a flip chip mounting method. Japanese Publication for Opposition No. 62-55721, for example, describes a conventional high frequency transistor employing the flip chip mounting.
FIGS. 18A to 18C are views showing the conventional flip chip mounting process according to the aforementioned Japanese Publication for Opposition. More specifically, FIG. 18A is a plan view showing the electrode structure of the high frequency FET disclosed in the aforementioned publication. FIG. 18B is a plan view of a package where the flip chip mounting is performed for the FET chip. FIG. 18C is a cross-sectional view showing a cross section taken along line 18C-18C' in FIGS. 18A and 18B.
In FIG. 18A, bumps 1511, 1512, and 1513 which are Au-plated so as to have a thickness of about 20 .mu.m are provided on a source electrode 1501, a gate electrode pad 1508, and a drain electrode pad 1509 in a high frequency FET chip 1510, respectively. A gate extension line 1505 connects a gate electrode 1502 with the gate electrode pad 1508, and a drain-gate extension line 1506 connects a drain electrode 1503 with the drain electrode pad 1509.
In FIG. 18B, a metal base 1515 has a convex portion 1519 (see FIG. 18C) on a surface 1515a (i.e., a principal surface 1515a) opposing the FET chip 1510. Alumina substrates 1516 are disposed at both sides of the convex portion 1519 of the metal base 1515. An input line 1517 or an output line 1518 are provided on each of the alumina substrates 1516.
In FIG. 18C, the bump 1511 on the source electrode 1501 is connected to the convex portion 1519 formed on the surface of the metal base 1515. The bump 1512 on the gate electrode pad 1508 is connected to the input line 1517 provided on one of the alumina substrates 1516. The bump 1513 on the drain electrode pad 1509 is connected to the output line 1518 provided on the other alumina substrate 1516.
The aforementioned Japanese Publication for Opposition No. 62-55721 states that (1) an improvement in the high frequency characteristics due to a reduction in the source inductance and (2) an improvement in the heat releasing property can be expected since the source electrode 1501 and the metal base 1515 can be connected to each other via the bump 1511 according to the above-described structure.
As another conventional technique employing the flip chip mounting, Japanese Laid-open Publication No. 5-190563, for example, describes a structure in which one bump is provided immediately above an actual operation region of a transistor element having multi-divided junctions.
In connection with a semiconductor device employing the flip chip mounting, which operates in a band from a quasi-millimeter wave to a millimeter wave, a technique called a millimeter-wave flip-chip IC (MFIC) is explained in the technical article entitled "A Novel Millimeter-Wave IC on Si substrate using Flip-Chip Bonding Technology" by H. Sasaki at al. (1994 IEEE MTT-S Digest, pp. 1763-1766). The MFIC technique employs a specific flip chip mounting technique called a microbump bonding method (also simply referred to as a "MBB method" in this specification).
Hereinafter, steps for fabricating a semiconductor device using the MBB method will be described with reference to FIGS. 19A to l9E which are cross-sectional views sequentially illustrating the fabrication steps employing the MBB method.
First, as shown in FIG. 19A, photocurable insulating resin 1625 is dropped onto a substrate 1621 with transmission lines 1622 provided thereon. Next, as shown in FIG. 19B, bumps 1624 provided on electrode pads 1623 of a semiconductor chip 1620 are aligned with electrode pads 1626 provided on the transmission lines 1622 on the substrate 1621 using a camera (not shown) or the like. Thereafter, as shown in FIG. 19C, the semiconductor chip 1620 is pressurized by a pressure jig 1627. By this pressurization, the photocurable insulating resin 1625 is eliminated between the bumps 1624 and the electrode pads 1626, and the bumps 1624 are compressed to be deformed and stuck into the electrode pads 1626. Consequently, the bumps 1624 are electrically connected to the electrode pads 1626. Next, as shown in FIG. 19D, ultraviolet rays 1628 are irradiated onto the photocurable insulating resin 1625 so as to cure the resin, thereby fixing the substrate 1621 with the semiconductor chip 1620. At this time, since the photocurable insulating resin 1625 shrinks, connection between the electrode pads 1623 and the electrode pads 1626 is further strengthened. Subsequently, as shown in FIG. 19E, after the photocurable insulating resin 1625 is cured completely, the pressure jig 1627 is removed. In this manner, mounting of the semiconductor chip 1620 onto the substrate 1621 is completed.
By using such a MBB method, the bump 1624 with a thickness of about several .mu.m or less can be obtained. As a result, parasitic inductance caused by the bumps 1624 can be suppressed to an extremely low level (i.e., an order of several picohenries (pH)), thereby obtaining a semiconductor device which can be satisfactorily used for a frequency in a millimeter wave band.
However, the high frequency transistors which are mounted using the flip chip mounting methods according to the conventional techniques as described above have the following problems.
First, the conventional high frequency transistor according to the Japanese Publication for Opposition No. 62-55721 described with reference to FIGS. 18A to 18C has problems as follows.
In FIG. 18C, in order to realize a stable and reliable mounting, it is necessary to equalize the height of the convex portion 1519 of the metal base 1515 with the heights of the lines 1517 and 1518 on the alumina substrates 1516 on the order of several .mu.m. In actuality, however, realization of such a setting is extremely difficult. As a result, it is hard to guarantee a stable production yield.
In addition, in order to further reduce a source inductance, it is necessary to reduce the parasitic inductance caused by the bump 1511. For that purpose, the height of the bump 1511 may be shortened. In such a case, however, a gate-source capacitance Cgs and a drain-source capacitance Cds are increased. In other words, according to the aforementioned conventional technique, it is difficult to realize the reduction in the source inductance and the reduction in the parasitic capacitance at the same time. Therefore, there is a limit to the improvement in the high frequency characteristics of the resultant device.
Moreover, since the source electrode 1501 of the FET chip 1510 is formed in an isolated manner, it is practically impossible to perform a DC (direct current) testing of the FET in a wafer state. The "DC testing" herein refers to a testing procedure for examining operation characteristics of the FET chip (e.g., a saturated drain current, a drain-source breakdown voltage, and the like).
More specifically, in order to perform the DC testing of the FET in a wafer state, a probe head must be in contact with all of the source electrodes 1501. However, the diameter of a commonly-used probe head for the DC testing is greater than the width of the source electrode 1501 (i.e., W shown in FIG. 18A is from about 15 .mu.m to about 30 .mu.m). Therefore, it is impossible to allow the probe head for the testing to contact all of the source electrodes. Thus, DC testing in a wafer state cannot be conducted. As a result, according to the conventional technique described above, screening of the FET chips cannot be performed by the DC testing in a wafer state. Thus, it is hard to realize an improvement in the production yield of the high frequency semiconductor device.
On the other hand, according to the structure disclosed in Japanese Laid-open Publication No. 5-190563, since an emitter electrode is formed so as to cover a wide area of a base electrode with an interlayer insulating film interposed therebetween, it is hard to reduce the base-emitter capacitance Cbe. As a result, there is a limit to the improvement in the high frequency characteristics. Moreover, although this conventional technique requires a bump having a thick film made of Au to be formed, the formation step therefor requires a relatively long period of time. Furthermore, since the amount of Au used is increased, the production cost is also raised.
Moreover, if the conventional MBB mounting method described with reference to FIGS. 19A to 19E is applied, for example, to the structure of the conventional high frequency semiconductor device shown in FIG. 17 or that shown in FIGS. 18A to 18C, a gate electrode and a drain electrode of a GaAs chip face a metal base in the thus obtained semiconductor device. As a result, parasitic capacitance component in the gate-source capacitance Cgs or the drain-source capacitance Cds is increased, thereby causing an adverse effect on the high frequency characteristics. Moreover, the distance between the FET chip and the metal base is likely to be varied upon mounting, the aforementioned capacitances Cgs and Cds are also varied, thereby resulting in variations in the high frequency characteristics due to the change in impedance.
As described above, according to the conventional flip chip mounting techniques (including the MBB method), it is difficult to fabricate a high frequency semiconductor device having well-satisfactory high frequency operation characteristics with an excellent yield.